The technology at issue in this case related to dynamic random access memory devices (DRAM). In DRAM storing information occurs when memory is “written” to the memory device and a “read’ operation is performed when memory is retrieved from the memory device. DRAM utilize a clock signal to execute the read and write signals, such that a previous “wait state” was no longer necessary. By removing the wait state processing speeds could increase without bottlenecking what data a processor could process. This enabled processors to perform a plurality of tasks by waiting a pre-determined number of clock cycles before executing a read or write operation.
Rambus is the assignee of United States Patent Number 7,287,109, which is directed towards methods of controlling data transfers associated with DRAM. In the ‘109 patent, a request packet includes control information indicating if the DRAM will perform a read or write operation, and a request packet that contains a delay value that indicates when the DRAM operation should be executed.
This case is an appeal that arises from an inter partes reexamination proceeding where the USPTO board affirmed an Examiner’s rejection under 35 USC 102(A) in view of US patent Number 6,584,037 (the Farmwald patent). Farmward was a patent that was filed before the ‘109 patent, which was also assigned to RAMBUS.
The Farmwald patent discloses access registers that store a set of one or more delay times at which a processor should be available to perform a read or write operation. In Farmwald, a controller transmits a request packet to the DRAM that includes a bit that selects an access time in the register. The memory device will then wait for the delay time associated with the bit that selects the register.
The Farmwald patent was 1) listed as prior art in the ‘109 patent stating that the predetermined set of registry delay values were inflexible because the start of an operation is tied to a predetermined number of clock cycles. Another patent by inventor Farmwald (United States Patent Number ‘5,319,755) was cited against the ‘109 patent during examination that had the same specification as the ‘037 patent, but was removed during examination via RAMBUS’ argument in a response to an office action. Further, during ITC investigations both Farmwald patents were cited against the ‘109 patent, where the ITC board concluded that the ‘755 Farmwald patent does not anticipate the ‘109 patent.
The court of appeals in this case reversed the Examiner’s and USPTO Board’s ruling that the Farmwald patent anticipates the ‘109 patent. The central issue of the case was associated with a limitation of the ’109 patent that recited “providing a signal to the memory device, wherein the signal indicates when the memory device is to begin sampling write data.” The court reasoned that the term “signal” in the claimed limitation does not cover “all signals” and only “a start indicator for the DRAM to being an operation” due to the clarification in the specification of the ‘109 patent. The court further held that the bit in Farmwald’s request packed does not include any timing information but merely selects an access-time register that subsequent events or signals cause a DRAM operation to begin. The court reasoned that the bit in the request does not include timing information and requires additional steps to be performed to determine the timing of the operation, and therefor Farmwald does not anticipate the ‘109 patent’s claims.
PATENT ATTORNEY TAKE-A-WAYS:
- This is a good case for Patent Attorney’s to site when an applicant’s invention reduces the amount of steps necessary to complete a procedure. Here, it appears that the crux of the argument was that by including the actual amount of time to delay the DRAM operation in the signal, RAMBUS could clarify that this is much more flexible and does not require 1) additional hardware (the time-bit registry), and 2) additional steps required of accessing the registry.
- In this case, the USPTO board stated that “skilled artisans would have considered… comparing Farmwald’s delay value to a clock value… as constituting providing a signal” as recited in claim 1 of the ‘109 patent. The Court of Appeals rejected the boards logic stating that the Board does not identify where Farmwald discloses this comparison, nor did the Board explain how “comparing” a delay value to a clock value equate to a “signal” under the construction that a “signal” means a representation of physical data. Therefore, this is a good case to site when an Examiner makes a conclusory statement without any backup evidence on their conclusion.
- In my opinion this is a very close case. I can definitely see how an Examiner would make the case that the timing bit in Farmwald meets a “signal indicates when the memory device is to begin sampling write data.” This is just because the timing signal in Farmwald does “indicate” when the memory device is to begin sampling write data, just it doesn’t “directly indicate.” If the claim language was written such as “wherein the signal indicates data associated with when the memory device is to begin sampling write data” it is likely the court would have found that Farmwald did anticipate this limitation of the claims. Therefore, may also be a good case to cite when examiners question if a claim limitation does not include language such as “associated with” or “based on” to show that a claimed element is “directly” performing an action without actually reciting “directly” in the claim limitation.